A semiconductor test device performs reading and writing of data with respect to each storage cell in a semiconductor memory (hereinafter simply referred to as “memory”) serving as a device to be tested (DUT), thereby analyzing failure of each storage cell. In general, the semiconductor test device compares data read out from the DUT and predetermined expected value data to perform judgment of pass/fail and stores a result of this judgment in a fail memory. Fail information stored in the fail memory in this way is collected by a fail analysis device constituted by a workstation and the like to investigate contents of the information, whereby various kinds of failure analysis with respect to this DUT is performed.
For example, the fail analysis device can display a fail distribution state of a large capacity DRAM as a physical map or a logical map by using a predetermined memory device evaluation tool. The physical map is a two-dimensional fail bit map using physical addresses X and Y as coordinates and is used for confirming a physical arrangement of failure storage cells of a memory. In addition, the logical map is a three-dimensional fail bit map using logical addresses X and Y and an I/O number as coordinates and may be four-dimensional in the case in which a logical address Z is used. This logical map is generated based upon fail information to be read out from the above-described fail memory.
Incidentally, a general semiconductor test device is capable of performing tests for a plurality of memories simultaneously, thereby realizing reduction of a test time for one memory. Therefore, when one test ends, fail information corresponding to each of the plurality of memories is stored in the above-described fail memory.
However, if a user attempts to cause the conventional fail analysis device to display contents of the logical map or the physical map in order to analyze the fail information obtained in this way, the user needs to specify a DUT in the first place. Therefore, in the case in which the user desires to know an outline of the fail information for the plurality of DUT which was objects of the test, the user needs to, after designating one DUT, repeat an operation for displaying contents thereof for each DUT. Thus, there is a problem in that complicated operations are necessary, operability is poor, and long time is required for the operations.
In particular, in the case in which the user displays contents of the logical map, the user needs to specify an I/O number together with a DUT. Therefore, in the case in which the user desires to look at an outline of fail information for one DUT, the user needs to, after designating one I/O number, repeat an operation for displaying contents thereof for each I/O number. Thus, operations become more complicated and long time is required for the operations.
In addition, since the user can only display contents of the physical map or the logical map by designating a DUT and the I/O number in the conventional fail analysis device as described above, when the user attempts to compare fail information of the respective DUTs for which the test was performed simultaneously or compare fail information of each I/O number of one DUT, the user needs to remember contents of each physical map or each logical map to be an object of comparison or to print the contents in a paper or the like. Thus, there is a problem in that it is not easy to grasp an outline of fail information for a plurality of DUTs or grasp an outline of fail information for a plurality of I/O numbers of each DUT.
In addition, in the above-described conventional fail analysis device, a detailed logical map or physical map is displayed by performing physical conversion processing based upon fail information read out from the fail memory in the semiconductor test device or using this fail information. Thus, in the case in which the user moves or enlarges a range of a logical map or a physical map to be an object of display, the user needs to read out the fail information from the fail memory in the semiconductor test device again. Therefore, there is a problem in that long time is required since the user instructs change of a display range until the display range is actually changed.
In addition, in the conventional fail analysis device, there is a problem in that an operation for instructing change of a display range is not easy and operability is poor. For example, in the case in which a reduced display screen containing a fail bit map corresponding to the entire DUT and a detailed display screen containing a detailed fail bit map corresponding to a part of the DUT can be selectively switched to be displayed, after confirming a detailed fail bit map of which part the user desires to look at with the reduced display screen, the user switches to a screen of this detailed fail bit map. In this case, if the user attempts to look at detailed fail bit maps of the other parts, the user needs to switch to the reduced display screen again. An operation becomes complicated because the user needs to switch the screens many times. In addition, although it is possible to display a detailed fail bit map of a part, which the user desires to look at, by scrolling displayed contents of the detailed display screen, the contents is not confirmed by alternately displaying the reduced display screen and the detailed display screen. Thus, it is not easy to find a fail part, which the user desires to look at next, by the scroll operation, and the scroll operation is repeated carelessly to some extent.
In addition, it is convenient if the logical map or the physical map generated by the above-described conventional fail analysis device can be superimposed with each other in the case in which tendencies of fail are compared, or the like. In the conventional fail analysis device, such superimposition of a plurality of bit maps is impossible, or it is possible only to perform simple superimposition under limitation. For example, even in the case in which superimposition of two fail bit maps is possible, these two fail bit maps are not associated with each other. Thus, if the user desires to perform superimposition by changing a display magnification again, the user needs to change the display magnification for each of the two fail bit maps. In addition, in the case in which the user desires to move a display area of the fail bit maps, since the two fail bit maps do not move in association with each other, the user needs to move the display area for each of the two fail bit maps. In addition, in the case in which the user performs superimposition by changing a combination of the plurality of fail bit maps, operations are repeated from reading of data for all the fail bit maps to be objects of superimposition every time the combination is changed. In addition, in the case in which the plurality of fail bit maps are superimposed, since only an order of superimposing them cannot be changed, a fail bit map is redrawn by changing the order. In this way, in the case in which superimposition of fail bit maps is performed using the conventional fail analysis device, there is a problem in that operations in performing some kind of change become complicated.
Further, in the case in which, for example, when two fail bit maps are compared, the user confirms to which degree fail parts coincide with each other, the user needs to perform an arithmetic operation of superimposed fail bit maps. However, in the conventional fail analysis device, it is impossible to perform such an arithmetic operation of fail bit maps.